Calibration of up and down charge-pump currents using a sample-and-hold circuit during idle times
US7034588B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2004 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Oct 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0896
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A charge pump for a phase-locked loop (PLL) has accurate matching of charge and discharge currents applied to the PLL's loop filter. A variable current-sink transistor has its gate-to-source voltage adjusted to match a source current from a fixed current source. An intermediate node in-between series transistors between the current source and sink is sampled by a sampling transistor that connects the intermediate node to a sampling capacitor. The sampling capacitor's voltage is the gate-to-source voltage of the variable current-sink transistor. The variable current-sink transistor has its gate and drain coupled together through the sampling transistor during calibration periods when the charge pump is otherwise idle. When the source current exactly matches the sink current, the gate-to-source voltage stored on the sampling capacitor reaches steady state. Up and down currents are balanced in driver transistors that match the series transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.