Dynamic phase alignment of a clock and data signal using an adjustable clock delay line
US7034597B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2004 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Oct 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.