Switching circuits
US7034609B2 · kind B2 · utility
13Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2003 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Nov 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45636
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique to implement removal of dead time control circuitry from the back-end of a digital switching amplifier system 100 and add dead time control circuitry on the front-end digital modulator chip. The front-end dead time control circuitry adaptively adjusts timing of the output PWM control signals 124 to optimize performance and power consumption, i.e. operate with minimum dead time for all transitions. The front-end dead time control circuitry controls all propagation delays associated with the digital switching amplifier system 100.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.