Image processing circuit
US7034868B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Feb 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel clock is switched to a high speed for reading culled pixel data from a CCD or switched to a low speed for reading all pixels from the CCD when picking up an image of an object, so that a main memory stores a first field initially read from the CCD and an RPU reads the first field from the main memory in synchronization with reading of a subsequent second field for executing a series of image processing in real time. The main memory stores the processed data. A CPU reads the processed data from the main memory, compresses the processed data and thereafter stores the same in a storage medium. Thus provided is an image processing circuit capable of increasing a frame rate for finder display and efficiently executing image processing at a high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.