Semiconductor memory device and semiconductor integrated circuit device
US7035128B2 · kind B2 · utility
10Cited by
6References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2003 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | May 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a DRAM memory cell including an access Tr and a cell capacitor, a depletion type MOSFET is used for each of the access Tr and the cell capacitor. Thus, an operation margin can be increased and the number of necessary power supplied can be reduced, compared to a known DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.