Memory architecture for increased speed and reduced power consumption
US7035132B2 · kind B2 · utility
5Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2003 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved multi-wordline memory architecture providing decreased bitline coupling to increase speed and reduce power consumption including an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.