SRAM-compatible memory device performing refresh operation having separate fetching and writing operation periods and method of driving the same
US7035133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | May 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM-compatible memory device performs a refresh operation with separate fetching and rewriting operation periods.The SRAM-conpatible memory device can be activated by a method of driving the SRAM-compatible memory device. During a first refresh period, the SRAM-compatible memory device performs an operation of fetching data from a DRAM cell to be refreshed. During a second refresh period, the SRAM-compatible memory device performs an operation of rewriting the data fetched during the first refresh period in the refreshed DRAM cell. Accordingly, the length of an assigned refresh period is reduced, and the length of an entire external access period is also reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.