Jitter measurement using mixed down topology
US7035325B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | May 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/205
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A jitter measurement method using a down-mixing or down-converting topology in a jitter measurement system preserves the jitter UI rather than the jitter seconds. An input serial data stream at a high baud is mixed with a stable local oscillator frequency that is close to that of the high baud. The difference between the high baud and the local oscillator frequency is passed by a filter as a lower rate serial stream. A clock recovery circuit recovers a lower rate clock from the lower rate serial stream, or an amplitude modulation removal stage converts the lower rate serial stream to a lower rate NRZ signal, or the lower rate serial signal is digitized. Jitter measurement is performed by a jitter measurement stage on the lower rate clock, the lower rate NRZ signal, or the digitized lower rate serial signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.