Automatic gain control loop apparatus
US7035351B1 · kind B1 · utility
6Cited by
60References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2000 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Jan 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/372
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A DC offset cancelling circuit with multiple feedback loops suppresses DC offset voltages within an automatic gain control loop apparatus. The apparatus includes a plurality of gain stages connected in series that receive and amplify an input RF signal. Each gain stage includes a corresponding feedback loop to filter the DC offset voltage accumulated in the respective gain stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.