High speed parallel link receiver
US7035368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Jun 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital system aligns a set of serial data receiver demultiplex circuits, thereby aligning the bits in the data words, while maintaining separate and optimally aligned data recovery clocks for each channel. The digital system generates a reference clock signal and one or more slave clock signals. Phase circuitry receives the slave clock signal and outputs a plurality of clock phase signals. A phase selection circuit receives the plurality of clock phase signals and selects an adjusted clock signal in response to a phase selection signal. A clock correlation circuit determines a phase difference between the reference clock signal and the adjusted clock signal and provides the phase selection signal to minimize the phase difference. The clock correlation circuit provides the phase selection signal from a counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.