Method for multiprocessor communication within a shared memory architecture
US7035908B1 · kind B1 · utility
4Cited by
23References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Nov 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of processors and a message circuit. The message circuit may be configured to pass messages between the processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.