Hardware implementation of an N-way dynamic linked list
US7035988B1 · kind B1 · utility
12Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2003 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Sep 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware-implemented N-way dynamic link list is disclosed. The linked list memory structure comprises two basic parts for each stored location (entry)—a data element and pointer to the next element. Separate memory components provide a data organization that efficiently accesses any of N queues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.