Converter circuit for synchronizing bus control signals according to a ratio of clock frequencies between different clock domains
US7036038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Aug 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A converter circuit for performing transfer of control logic signals between a first device and a second device in connection with an interconnection bus, the first device operating at the frequency of a first clock signal and the second device operating at the frequency of a second clock signal. The clock frequencies may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The converter circuit includes manipulation circuit elements which define respective propagation paths through the converter circuit for control signals. A logic network may assume three states, corresponding, respectively, to the first, second and third ratios between the frequencies of the clock signals, selectively interposing the manipulation elements in the propagation paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.