Two dimensional data eye centering for source synchronous data transfers
US7036053B2 · kind B2 · utility
48Cited by
5References
36Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 19, 2002 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | May 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.