Patent · US Expired

Structural input levels testing using on-die levels generators

US7036061B2 · kind B2 · utility

7Cited by
8References
23Claims
0Family size

Assignee

Inventor

Key dates

Filing dateAug 28, 2001
Grant dateApr 25, 2006
Priority date—
Expiry dateOct 30, 2022

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318572
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A set of levels generating circuits, such as a set of digital-to-analog converters, is designed into an integrated circuit on-die. The levels generating circuits apply direct current (DC) voltage levels to on-die sense amplifiers to test sense amplifier trip points for “input low voltage” (VIL) and “input high voltage” (VIH). The levels generating circuits are controlled by a set of configuration bits, which may be accessible through the boundary-scan register or the input/output (I/O) loop back pattern generator. The levels generating circuitry allows testing of one number of integrated circuit input pins using a smaller number of input pins.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.