Manufacturing method of semiconductor device
US7037788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2004 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | May 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/2527
Abstract
By improving profile of impurity concentration in a channel portion of an FET or an IGBT of a trench gate type, variation of threshold value is lessened, and a destruction caused by current concentration is prevented while suppressing deterioration of cut-off characteristics. An island of a base region of p-type is formed in a semiconductor substrate of n-type by carrying out high acceleration ion implantation twice followed by annealing, so that the impurity concentration profile in a channel portion changes gradually in a depth direction. Accordingly, it is possible to lessen variation of the threshold value and to reduce pinch resistance while at the same time improving sub-threshold voltage coefficient and conductance characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.