Apparatus and method for staircase raised source/drain structure
US7037818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2004 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Aug 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure, apparatus and method for improving the performance of semiconductor devices is provided. The semiconductor structure includes a raised source/drain region above a planar source/drain. The raised source/drain has at least a first step and a second step with a variety of transitions therebetween. The first step is of a prescribed height configured to optimize performance of the semiconductor device and is arranged next to a gate. The first step has a top surface above a lower surface of the gate. The second step is arranged next to the first step and has an upper surface raised above the upper surface of the first step. The raised source/drain is configured to reduce resistance with a minimal increase of gate capacitance. The raised source/drain may be fabricated in one deposition step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.