Integrated circuit bond pad structures and methods of making
US7038280B2 · kind B2 · utility
54Cited by
12References
37Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Oct 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.