Enhanced efficiency feed forward power amplifier utilizing reduced cancellation bandwidth and small error amplifier
US7038540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2004 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Feb 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/3247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A feed forward power amplifier is disclosed which utilizes three signal cancellation loops. Loop 1 includes a main amplifier and is used to derive a carrier cancelled sample of the main amplifier output. Loop 2 includes an error amplifier used to amplify the carrier cancelled signal derived from Loop 1 operation in order to cancel distortion products generated due to the nonlinear nature of the main amplifier. Loop 2 also utilizes a very short Loop 2 delay line. A significant efficiency gain is provided due to reduced output power losses associated with the Loop 2 delay line. Lower output losses also results in lower distortion levels produced by the main amplifier. This, in turn, reduces the size and performance requirements placed on the error amplifier. A smaller and more efficient error amplifier is employed resulting in further amplifier system efficiency improvement. A spurious signal detector for out-of-band distortion detection and an associated microcontroller for Loop 1 and Loop 2 control are also provided. A third signal cancellation loop is utilized to sample the amplifier output and reduce the carrier level of the signals sampled at the output of the amplifier before p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.