High performance computer system having a firmware error queue and automatic error handling
US7039836B2 · kind B2 · utility
14Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Oct 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cellular computer system is constructed of a plurality of cells. Each cell has a memory system, a plurality of processors capable of accessing the memory system, a system communication interface coupled to processors, and a cell error queue maintained by a processor within the memory system. The system communication interface of each cell is coupled to other cells of the system. A first cell of the plurality of cells is a master cell that maintains a partition error queue and is capable of receiving into the partition error queue error descriptors from the cell error queue of a second cell of the plurality of cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.