Method and apparatus for high update rate integrated circuit boundary scan
US7039840B2 · kind B2 · utility
1Cited by
2References
5Claims
0Family size
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Key dates
| Filing date | Apr 9, 2003 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Jul 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Boundary scan cells for driving internal logic and sensing internal logic of integrated circuit use external clocks synchronized with internal functional clocks. Synchronized clocks enable synchronous sampling of internal signals and synchronized of injection signals into a functional portion of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.