Convolutional encoding using a modified multiplier
US7039852B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | May 2, 2006 |
| Priority date | — |
| Expiry date | Dec 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/23
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wireless communications device is disclosed, in which certain digital coding functions are realized according to a modified multiplier architecture. The device includes an encode and modulate function within which convolutional coding function is provided. The convolutional coding function may be realized as a modified parallel multiplier, in which carries among adder units are ignored or not generated. The datastream is applied to the multiplier as the multiplicand, while successive sets of code generator polynomial coefficients are applied as a multiplier. Carry-in and carry-out bits among the adder units are blocked in a coding mode, but passed in a multiplier mode. A similar arrangement of a modified parallel multiplier circuit may be used in generating a scrambling code that is applied prior to transmission.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.