High density memory array
US7042030B2 · kind B2 · utility
7Cited by
12References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Apr 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory array contains two layers representing word lines of different rows. Each row contains multiple bit cells sharing the same word line. The two layers are stacked one on top of another to form a high density memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.