Method for packaging electronic modules and multiple chip packaging

US7042085B2 · kind B2 · utility

Assignee

• Robert Bosch GmbH · DE

Inventors

• Kuno Wolf · Hechingen, DE
• Stephan Ernst · Esslingen am Neckar, DE
• Robert Plikat · Eningen unter Achalm, DE
• Wolfgang Feiler · Reutlingen, DE

Key dates

• Filing date: Sep 26, 2002
• Grant date: May 9, 2006
• Expiry date: Sep 26, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for packaging electronic assemblies and a multiple chip package, at least one power semiconductor chip being applied to a base plate using a first solder, at least one logic chip being applied to the base plate, the logic chip and the base plate being positioned electrically insulated from one another, at least one logic chip being connected to the at least one power semiconductor chip using signal transmission lines, and the electronic assembly including the at least one power semiconductor chip and the at least one logic chip being packaged using a molding compound in order to provide a multiple chip package.