Stacked semiconductor module and assembling method of the same
US7042086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Oct 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor module encompasses (a) a upper switching element having a first semiconductor chip, a first top electrode disposed at a top surface of the first semiconductor chip, a first bottom electrode disposed at a bottom surface of the first semiconductor chip, and a first control electrode configured to control conduction between the first top and first bottom electrodes; (b) a first wiring plate disposed beneath the upper switching element, electrically connected to the first bottom electrode; and (c) a lower switching element disposed beneath the wiring plate, having a second semiconductor chip, a second top electrode disposed at a top surface of the second semiconductor chip, electrically connected to the first wiring plate, a second bottom electrode disposed at a bottom surface of the second semiconductor chip, and a second control electrode configured to control conduction between the second top and second bottom electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.