Memory clock slowdown synthesis circuit
US7042263B1 · kind B1 · utility
13Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Dec 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.