Circuit and method for reducing jitter in a PLL of high speed serial links
US7042277B2 · kind B2 · utility
7Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Oct 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.