Delay equalized Z/2Z ladder for digital to analog conversion
US7042381B1 · kind B1 · utility
7Cited by
2References
13Claims
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Key dates
| Filing date | Jan 13, 2005 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Jan 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.