High speed gain amplifier and method in ADCs
US7042383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2004 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Nov 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.