Method and circuit for dynamic read margin control of a memory array
US7042776B2 · kind B2 · utility
12Cited by
17References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2004 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Feb 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.