Dynamic selection of lowest latency path in a network switch
US7042891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2001 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | May 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for low latency switching of data packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Under normal operation, the data transport logic stores packet data into the memory. Later, the packet data is read from the memory and output to a destination output port. To reduce latency when the switch is not congested, the switching logic may be configured to perform a cut-through operation by routing packets directly from input ports to output ports without storing any portion of the packet in the memory. Alternatively, the switch may begin forwarding the stored packet data to the output port before the entire packet has been received or stored in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.