Method and apparatus for interfacing multiple communication devices to a time division multiplexing bus
US7042895B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1999 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Sep 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13299
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A time division multiplexing (TDM) method and apparatus for interfacing data from communication channels to a TDM bus. The TDM arrangement uses a shift register to control a tri-state buffer. The shift register regulates the tri-state buffer based on a data bit pattern loaded into the shift register. The data bit pattern corresponds to the status of the individual channels. Each channel is assigned a bit which indicates whether the channel is active or inactive. As the shift register shifts out data, the tri-state buffer allows data to flow onto the TDM bus when a bit indicating an active channel is present and insulates the TDM bus from the communication channels when a bit representing an inactive channel is present. A processor is used to control the interrelationship of the multiple communication channels and to generate the status bits to be loaded into the shift register. The processor fills the shift register through the use of a storage register. In a preferred embodiment, the shift register is capable of shifting out a sufficient number of bits to fill an entire transmission frame operating in T1 (24 channels), E1 (32 channels), 64-slot (64 channels), and 128-slot (128 cha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.