Soft bit computation for a reduced state equalizer
US7042938B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2001 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | May 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0342
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for soft bit computation with a reduced state equalizer. The method assures that the number of states in the equalizer is reduced to obtain acceptable complexity, while also ensuring that soft bit computation is performed for substantially all bits. The method involves computing a first set of soft bits from bits transmitted in a received signal, using a reduced-state trellis with finite non-zero delay, calculating hard decisions in response to the received signal, and also ensuring that substantially all soft bits are computed by employing zero-delay soft decision-making or decision-feedback equalization to compute a second set of soft bits. Furthermore, the hard decisions are used to compute the second set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.