Phase frequency detector with adjustable offset
US7042970B1 · kind B1 · utility
16Cited by
13References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2001 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Jul 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the first being clocked with the reference signal and the second with the loop feedback signal. The output of the second flip-flop is delayed relative to the first flip-flop, thereby effecting minimal overlap, when using the phase detection apparatus in a fractional- N phase lock loop, of the interpolator activity with that of the charge pump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.