Reduction of add-pipe logic by operand offset shift
US7043516B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Mar 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The shifters (30, 32) that a floating-point processor (10)'s addition pipeline (14) uses to align or normalize floating-point operands' mantissas before addition or subtraction shift a given mantissa pair one more bit to the left for subtraction than for addition. As a result, the addition pipeline's rounding circuitry (160, 166) does not need to be capable of adding round bits in as many positions as it would without the shift difference, so it can be simpler and faster. Similarly, circuitry (164a–g and 188) employed for normalization after addition and subtraction can be simpler because it does not have to implement as shift options.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.