Multiply accumulator for two N bit multipliers and an M bit addend
US7043517B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 7, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Oct 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply accumulator performs a multiplication-and-addition operation for a first multiplier with N bits, a second multiplier with N bits, and an addend with M bits, wherein M is larger than 2N. The multiply accumulator includes a modified Booth encoder and a multiplication-and-addition unit. The modified Booth encoder performs a Booth encoding to either the first multiplier or its bit inversion by supplementing a multiplier sign bit behind a least significant bit of either the first multiplier or its bit inversion. The multiplication-and-addition unit includes a carry save adder tree and a sign extension adder and achieves a high speed of the multiplication-and-addition operation by simultaneously performing the multiplication and addition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.