Self-nesting interrupts

US7043582B2 · kind B2 · utility

Assignees

• Intel Corporation · US
• Analog Devices, Inc. · US

Inventors

• Ravi P. Singh · Austin, US
• Thomas Tomazin · Austin, US
• Charles P. Roth · Austin, US
• Jose Fridman · Brookline, US
• Michael S. Allen · Union Gap, US

Key dates

• Filing date: Sep 6, 2002
• Grant date: May 9, 2006
• Expiry date: Mar 31, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/4812
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.