Priority encoder circuit and method
US7043601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2003 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Nov 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for high speed generation of a global address corresponding to the highest priority active matchline sense output signal received after a CAM search-and-compare operation is disclosed. A priority encoder having blocks of multiple match resolver circuits arranged in a logical order of priority receives a plurality of active matchline sense output signals. Each block of multiple match resolver circuits generates a flag signal and a local address corresponding to the highest priority active matchline sense output signal received. Control logic receives flag signals from the multiple match resolver circuits, and identifies the highest priority multiple match resolver circuit that has received an active matchline sense output signal. The control logic then disables all lower priority multiple match resolver circuits such that only the local address generated by the highest priority multiple match resolver circuit is passed by the priority encoder. The flag signals are also decoded to provide a logical address of the highest priority multiple match resolver circuit. The passed local address and the logical address of the highest priority multiple match resolver circui…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.