Method for early evaluation in micropipeline processors
US7043710B2 · kind B2 · utility
10Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2004 |
| Grant date | May 9, 2006 |
| Priority date | — |
| Expiry date | Nov 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for early evaluation in micropipeline processors to improve performance is provided. The present invention presents a design methodology where a micropipeline processor block (e.g., a binary full adder) is capable of computing a result based on the arrival of only a subset of inputs. In general, early evaluation allows micropipeline processor blocks to operate in parallel, where they might otherwise operate sequentially because of data arrival dependencies; thereby improving performance of the micropipeline processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.