Stacked die package
US7045390B2 · kind B2 · utility
4Cited by
19References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Jan 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3478
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked die package is formed by stiffening a flexible substrate, arranging a chip mounting pattern on one side of the substrate, and mounting chips according to the arranged pattern. A solder ball array on the opposite side of the substrate is routed to the chips, and the flexible substrate and stiffener are folded to align the chips in the stacked die package. The stiffener is removed by a single saw cut.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.