Scanning image employing multiple chips with staggered pixels
US7045758B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2005 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Apr 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/806
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.