Delayed-locked loop with fine and coarse control using cascaded phase interpolator and variable delay circuit
US7046058B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Dec 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay-locked loop (DLL) circuit includes a phase interpolator circuit and variable delay circuit coupled in cascade and operative to generate an output clock signal that is delayed with respect to a reference clock signal responsive to respective first and second control signals applied to the phase interpolator and the variable delay circuit. The DLL circuit further includes a phase control circuit that generates the first and second control signals responsive to the output clock signal and the reference clock signal. The variable delay circuit may provide a coarser resolution than the phase interpolator circuit, for example, the variable delay circuit may include a tapped delay chain circuit configured to provide step changes in delay responsive to the second control signal. The phase control circuit may be operative to cause the phase interpolator circuit to shift from one extreme of a delay range thereof towards another extreme of the delay range concurrent with a step change in delay through the variable delay circuit to thereby limit overcompensation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.