Method and/or apparatus for generating a write gated clock signal
US7046066B2 · kind B2 · utility
12Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2004 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Jun 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.