Patent · US Expired

Apparatus and method for on-chip ADC calibration

US7046179B1 · kind B1 · utility

37Cited by

6References

26Claims

0Family size

Assignee

NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

Robert C. Taft · Munich, DE
Christopher A. Menkus · Munich, DE
Maria R. Tursi · Munich, DE
Ols Hidri · Munich, DE
Andreas Tuechler · Eppelheim, DE
Valerie Pons · Munich, DE

Key dates

Filing date	Mar 30, 2004
Grant date	May 16, 2006
Priority date	—
Expiry date	Mar 30, 2024

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/12
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An ADC circuit includes a multiplexer, a calibration circuit, one or more ADC banks, and a calibration ladder, all on an integrated circuit. The calibration resistor ladder is enabled during a calibration phase, and disabled during normal operation. When enabled, the calibration resistor ladder provides a calibration reference signal. Also, the multiplexer provides the calibration reference signal to one or more ADC banks during a calibration phase, and provides an analog input signal to the ADC banks otherwise. The calibration circuit is arranged to provide one or more adjustment signals to the ADC banks to calibrate the ADC banks in response to one or more comparator output signals from the ADC banks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.