Arrangements of clock line drivers
US7046283B1 · kind B1 · utility
13Cited by
26References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Dec 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/153
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a circuit chip and a plurality of clock drivers external to the circuit chip. The circuit chip includes a plurality of isolated clocking subunits and a corresponding plurality of terminals. Each clocking subunit is electrically isolated from any other clocking subunit. Each clocking subunit is coupled to a respective terminal. For each of the plurality of terminals, an output from one and only one clock driver of the plurality of clock drivers is coupled to the corresponding terminal of the plurality of terminals, and inputs of all clock drivers are coupled together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.