Vertical synchronous signal detection circuit
US7046301B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Oct 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A vertical synchronous signal detection circuit includes an analog-digital converter, an average calculation circuit and a compare circuit. The analog-digital converter receives a composite video signal and converts the video signal into a digital signal having a vertical synchronizing pulse. The average calculation circuit is coupled to receive the digital signal. The average calculation circuit calculates an average level of the vertical synchronizing pulse within a predetermined period. The compare circuit is connected to the average calculation circuit. The compare circuit compares a threshold level received thereto with the average level and outputs a synchronous detect signal when the average level falls below the threshold level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.