Noise reduction circuit
US7046304B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Oct 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/144
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A noise reduction circuit comprises correlation value calculation means for calculating correlation values in a plurality of directions centered at a pixel to be corrected; correction amount calculation means for calculating, on the basis of the correlation values in the plurality of directions calculated by the correlation value calculation means, a correction amount corresponding to the pixel to be corrected for each of the directions; first correction value calculation means for producing a plurality of candidates for correction values corresponding to the pixel to be corrected on the basis of the correction amount for each of the directions which is calculated by the correction amount calculation means; and second correction value calculation means for calculating the correction value for the pixel to be corrected from the plurality of candidates for correction values corresponding to the pixel to be corrected which are produced by the first correction value calculation means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.