Nonvolatile memory structure
US7046549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Jun 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.