Reporting a saturated counter value
US7047270B2 · kind B2 · utility
4Cited by
4References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2002 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Sep 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.