Method and apparatus for dynamic timing of memory interface signals
US7047384B2 · kind B2 · utility
35Cited by
11References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 27, 2002 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Sep 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.